Virtual Unit Delay for digital frequency adaptive T/4 Delay Phase-Locked Loop system

Digital micro-controllers/processors enable the cost-effective control of grid-connected power converter systems in terms of system monitoring, signal processing (e.g., grid synchronization), control (e.g., grid current and voltage control), etc. Normally, the control is implemented in a micro-controller/processor with a fixed sampling rate considering the cost and complexity, where the number of unit delays that have been adopted should be an integer. For instance, in conventional digital control systems, a single-phase T/4 Delay Phase-Locked Loop (PLL) system takes 50 unit delays (i.e., in a 50-Hz system with a sampling frequency of 10-kHz) to create a 90¿¿-lagging voltage in order to achieve the grid synchronization with the orthogonal voltage system. However, in practice, the grid frequency is a time-variant parameter due to various eventualities, and thus rounding the number of the unit delays for the T/4 Delay PLL system should be done in its implementation. This process will result in performance degradation in the digital control system, as the exactly required number of delays is not realized. Hence, in this paper, a Virtual Unit Delay (VUD) has been proposed to address such challenges to the digital T/4 Delay PLL system. The proposed VUD adopts linear interpolation polynomial to approximate the fractional delay induced by the varying grid frequency in such a way that the control performance is enhanced. The proposed VUD has been demonstrated on a digitally controlled T/4 Delay PLL system. Experimental results have confirmed the effectiveness of the proposal.