Uniformity of device performance improvement for the SOT-MRAM by optimizing the lithography process at 200-mm-wafer manufacturing platform

We examined the influence of process uniformity on the device performance for the spin-orbit torque (SOT) magnetic random access memory (MRAM) devices. By optimizing the lithography process through changing the multi-energies exposure compensation and pretreatment in developing, we demonstrated 1.6 times sigma improvement of the critical dimensions (CD), leading to 49.5%, 54.2%, and 63.2% sigma% reduction for SOT channel resistance (R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</inf> ), magnetic tunnel junction (MTJ) resistance (R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</inf> ) and switching current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</inf> ) respectively. These promising results will help to deliver SOT-MRAM to the mass manufacturing in the semiconductor industry.