Topological generation and analysis of voltage multiplier circuits

Voltage multipliers are used for transformerless conversion of an ac input voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\upsilon_i(t)= E \sin \omega t</tex> into a dc output voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{out} = nE</tex> , where <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n \geq 2</tex> . This paper investigates the topological properties of voltage multiplier circuits and presents a unified approach for generating new voltage-multiplier circuit structures. In particular, an algorithm is presented for generating <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> -fold voltage multipliers with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> capacitors and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> diodes. A theorem is presented for finding the dc capacitor voltages by inspection when no load current is drawn. For the case with load, explicit formulas for the output de voltage and the output resistance are given. Using the algorithm developed in this paper, three new voltage quadrupler circuits are generated and shown to have an output resistance only one-half of the conventional ladder quadrupler circuit.