Thermal Stress Mapping of Power Semiconductors in H-bridge Test Bench

As thermal stress of the power semiconductor is an important indicator for reliable power converter operation, the mapping of the junction temperature is becoming crucial need. In this paper, the loss dissipation and thermal stress of the power semiconductor are investigated in the universal H-bridge test bench. It starts with its basic operation principle. Based on the loss and thermal model of the power semiconductor, dominating factors (e.g. power factor, loading current amplitude, fundamental frequency, and switching frequency) impact on the loading stress of the power semiconductors are considerably investigated. Finally, the junction temperature of the power device in terms of the mean vale and temperature swing is verified in PLECS simulation and experimental setup.