The Research and Simulation of Synchronization Algorithms of GBPS Parallel Digital Receiver

In response to the development of future remote sensing satellites transmission, the parallel structure of the digital receiver should be adopted under the current hardware limitation of the-state of art of the FPGA. A parallel timing recovery algorithm and a parallel carrier recovery algorithm are proposed in this paper. The simulation and implementation results show that the proposed parallel digital receiver is capable for the Gbps demodulation. The structure has lower complexity for implementation compared to the PRX and APRX.