SP 22.4: A 1V 0.9mW at 100MHz 2kx16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25pm Dual-Vt CMOS

T. Moriis; Mark Horowitz; I. Fukush; T. Izawa; S. Mitarai

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SP 22.4: A 1V 0.9mW at 100MHz 2kx16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25pm Dual-Vt CMOS

Article 1998 English

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SP 22.4: A 1V 0.9mW at 100MHz 2kx16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25pm Dual-Vt CMOS

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SP 22.4: A 1V 0.9mW at 100MHz 2kx16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25pm Dual-Vt CMOS

A 1 V 0.9 mW at 100 MHz 2 k×16 b SRAM utilizing a half-swing pulsed-decoder and write-bus architecture in 0.25 μm dual-Vt CMOS

Crystal structure of low-potential cytochrome c 549 from Synechocystis sp. PCC 6803 at 1.21 Å resolution

A novel monolithic ultraviolet image sensor based on a standard CMOS process

Thermal error analysis and compensation of a LED-CMOS camera 3D measuring system