Sample stage induced dose and energy nonuniformity in plasma immersion ion implantation of silicon

Plasma immersion ion implantation has been demonstrated to be a viable technique for microelectronics processing such as fabrication of shallow junction and silicon on insulator. However, a wider acceptance of this fledgling technology by the semiconductor industry is not possible unless the stringent dose and energy uniformity requirements can be met. We have recently discovered that the lateral dose and energy nonuniformity that is unacceptable to the silicon industry stems from the insulating shroud commonly used around the sample stage to reduce the current demand on the power supply. We have developed a theoretical model to explain the experimental results. The model can also be used to optimize the operating conditions and equipment design to achieve the desired dose and energy uniformity across a planar silicon wafer to satisfy the semiconductor industry.