Performance Evaluation of Three-Level Z-Source Inverters Under Semiconductor Failure Conditions

This paper proposes various compensation methods for three-level Z-source inverters under semiconductor failure conditions. Unlike the traditional fault tolerant techniques in three-level inverter by using either an additional phase-leg or collective switching states, the proposed methods simply reconfigure the gating signals in order to tolerate the failed semiconductor devices without significantly decreasing the ac output quality and amplitude by properly using the inherent boost characteristic of Z-source network. In addition, the Z-source dual inverters can maintain the zero common mode voltage under semiconductor failure conditions, which is the unique characteristic attained by the dual inverters only. Lastly, all theoretical findings are verified in PLECS simulations.