Performance evaluation of a 15-level inverter using two DC sources with lower standing voltage

Most of the reduced switch multilevel inverters (MLIs), including switched capacitor MLIs (SC-MLIs), are designed with voltage sources/capacitors have obtained voltage levels with the addition of these sources only. This increases the number of voltage sources (capacitors) without full utilisation of these sources and has higher inverter total standing voltages, which leads the inverter inefficient (high conduction loss) and costly. The motivation of this work is to design a generalised reduced component MLI aiming for addition as well as subtraction of the voltage sources to obtain a voltage level, which results in the reduction of sources, enhance the voltage utilisation and lowering the inverter total standing voltage (TSV). The design parameters of the proposed MLI topology are compared with the recently developed MLIs in terms of the number of switches, capacitors and TSV to prove its superiority. The experimental prototype of the specimen 15-level and 27-level inverters is implemented using DS1103 and the corresponding results are presented.