Parallel interleaved inverters for reactive power and harmonic compensation

This article investigates the concept of paralleling power inverters for reactive power and harmonic compensation. The investigation focuses on a topology that shares the dc-bus capacitor between two parallel interleaved inverters. The advantages of the proposed approach are: i) decreased current ripple or use of lower switching frequency due to the interleaving, ii) reduced stress in dc-link capacitor due to the shared connection, iii) efficient implementation for high power applications because of paralleling. Different comparisons between the selected topology and regular power converters are discussed. Practical tests, on a three-phase 5 kVA, 400 V prototype, are presented to validate the analysis.