Implementation of High Speed Pipelining FFT Algorithm Based on FPGA

The paper proposes the implement scheme of the 1024 points radix-4 DIT FFT algorithm on FPGA.The butterfly unit,which is the core of the algorithm,is analysed and optimized.Due to timing controlling,the developed butterfly unit uses only one complex multiplier and has the same efficiency to the three multiplier structure.The processor is working in pipeline,which made the implement of the FFT algorithm on FPGA is both area and speed efficient.The simulation result is presented in the last section and compared with the FFT result using MATLAB.It shows that the total simulation time of the 1024 points FFT is 51.28 μs when operated at 100 MHz clock,which well meets the demands of high speed FFT alogrithm.