Hybrid HCI Degradation in Sub-micron NMOSFET due to Mixed Back-end Process Damages

This paper presents one hybrid hot carrier injection (HCI) degradation behavior of 3.3 V NMOS transistor. It is noted to remarkably occur when annealing the wafer fully encapsulated by the passivation layer (as enclosed in the red box in Fig. 1). Along with the HCI stress time, the degradation mechanism transits from the drain avalanche hot carrier (DAHC) injection to the channel hot electron (CHE) injection, manifesting as the turn-around behavior of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dsat</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Tsat</sub> degradation. Electrical stress test results indicate the weak gate oxide interface with silicon substrate. It could be attributed to the combined contribution of the plasma induced damage (PID) in high density plasma (HDP) deposition and the hydrogen species driven to the gate oxide interface by the alloying process. The results in this work can inspire the HCI tuning regarding back-end process steps.