Harmonic Optimization Strategy for CPS-PWM Based MMCs Under Submodule Capacitor Voltage Reduction Control

A submodule (SM) capacitor voltage reduction control (SCVRC) can reduce voltage stress of power devices and capacitors in a modular multilevel converter (MMC) and also improve reliability. However, the SCVRC may deteriorate the harmonic performance of the MMC's output. This article proposes a harmonic optimization strategy for the carrier phase-shifting pulsewidth modulation-based MMCs under SCVRC. It can improve the harmonics of the MMC through adjusting the phase-shift angle between the upper arm carriers and the lower arm carriers of the MMC and the SM capacitor voltage of the MMC to their optimal values, which can be derived based on the SM number per arm, rated SM capacitor voltage and modulation index. The proposed harmonic optimization strategy can ensure that the MMC not only works at low capacitor voltage but also works without deteriorating the harmonic performance. Simulations and experiments are conducted, and their results confirm the effectiveness of the proposed strategy.