Fisherman learning algorithm of the SOM realized in the CMOS technology

This study presents an idea of transistor level realization of the sherman learning algorithm of Self-Organizing Maps (SOMs) which is described in (4). The realization of this algorithm in hardware calls for a solution of several specic problems not present in software implementa- tion. The main problem is related to an iterative nature of the adaptation process of the neighboring neurons positioned at particular rings surround- ing the winning neuron. This makes the circuit structure of the SOM very complex. To come up with a feasible realization, we introduce some mod- ications to the original sherman algorithm. Detailed simulations of the software model of the SOM show that these modications do not have the negative impact on the learning process, and helps bring signicant reduc- tion of the circuit complexity. In consequence, a fully parallel adaptation of all neurons is possible, which makes the SOM very fast.