Evaluation of circulating current suppression methods for parallel interleaved inverters

Two-level Voltage Source Converters (VSCs) are often connected in parallel to achieve desired current rating in multi-megawatt Wind Energy Conversion System (WECS). A multi-level converter can be realized by interleaving the carrier signals of the parallel VSCs. As a result, the harmonic perfor-mance of the WECS can be significantly improved. However, the interleaving of the carrier signals may lead to the flow of circulating current between parallel VSCs and it is highly desirable to avoid/suppress this unwanted circulating current. A comparative evaluation of the different methods to avoid/suppress the circulating current between the parallel interleaved VSCs is presented in this paper. The losses and the volume of the inductive components and the semiconductor losses are evaluated for the WECS with different circulating current suppression methods. Multi-objective optimizations of the inductive components have been also carried out. The design solutions, that are obtained using the optimization, have been compared on the basis of the volume of the inductive components and yearly energy loss for a given mission profile.