Energy-Efficient Processor Design

 Acknowledgments  This work was performed in collaboration with Aqeel Mahesri and Sanjay Patel from the University of Illinois at Urbana-Champaign  Related References  Omid Azizi; Mahesri, A.; Patel, S.; Horowitz, M., “Area-Efficiency in CMP Core Design: Co-optimization of Circuits and Microarchitecture,” Workshop on Design, Architecture, and Simulation of Chip Multiprocessors (dasCMP), 41st International Symposium on Microarchitecture, November 2008.  Omid Azizi; Collins, J.; Patil, D.; Wang, H.; Horowitz, M., “Processor Performance Modeling using Symbolic Simulation, IEEE International Symposium on Performance Analysis of Systems & Software, 2007. ISPASS 2008. 20-22 April 2008. Architectural Performance Modeling and Optimization