Digital Phase-Frequency Detector in All-Digital PLL-based Local Oscillator for Radio Frequency Identification System Transceiver

An all-digital phase locked loop (A-DPLL)-based frequency synthesizer of the local oscillator (LO) for the radio frequency (RF) transceiver application such as in radio frequency identification (RFID) system has gained popularity among academia due to the transition of circuit technology from analog to digital implementation by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. The phase-frequency detector (PFD) is one of the main blocks in ADPLL and it is capable to detect the presence of phase and frequency errors by recognizing two input signals in digital form. The full-ranged of a time-to-digital converter (TDC) is commonly used in PFD block, but the power consumption is high. In this work, the less-TDC will be designed in the digital PFD block as an early development stage design for the ultra-low power ADPLL in order to improve fast phase-frequency acquisition and reduce power consumption. The digital PFD is designed by using Matlab Simulink and Verilog Hardware Description Language (HDL) code. The simulation result obtained that the time difference of the input signals for the Verilog is smaller than the result in Matlab Simulink without a unit delay. Thus, the design of the digital PFD will lead the desired ADPLL to achieve ultra-low power and fast locking range for RFID application.