Design of efficient multiplierless FIR filters

An algorithm for reducing the hardware complexity of linear phase finite impulse response digital filters that minimise the adder depth in the multiplier block adders (MBAs) is presented. The algorithm starts by aggressively reducing both the coefficient wordlength and the number of non-zero bits in the filter coefficients. This reduces the number of adders (the adder depth) that are needed to construct the coefficient multiplier and results in an increased operating frequency. A modification to the representation of the filter coefficients such that the number of full adders (FAs) in our hardware implementation is proportional to the product of the input signal wordlength and the number of adders is proposed. That is, in general, the number of FAs is independent of the coefficient wordlength and the number of shifts between non-zero bits in the coefficient. Results show that the proposed technique achieves a 67 and 70% reduction in the number of MBAs and the number of multiplier block FAs, respectively. A software program has been implemented, which generates a Verilog HDL description of the digital filter. The proposed technique is not limited to filters with only a small number of taps and has been successfully applied to filters with up to 500 taps.