Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach

A phase-locked loop (PLL) and delay-locked loop (DLL) design with adaptively adjusting bandwidth enables optimal performance over a wide frequency range and across process, voltage, and temperature variations. A design methodology of such adaptive-bandwidth PLLs and DLLs is described. To assess the impact of each circuit parameter directly, we derive a discrete-time, open-loop dynamic model of the PLL/DLL that characterizes the change in output variables in response to the sampled error and we express the adaptive-bandwidth criteria in terms of the open-loop gains, instead of the traditional closed-loop parameters, /spl omega//sub n/ and /spl zeta/. Applying these criteria, we derive scaling equations for the charge-pump current and filter resistance that achieve adaptive bandwidth in charge-pump PLL/DLLs. We show that previously published adaptive-bandwidth PLL/DLLs, a self-biased PLL/DLL and a regulated-supply PLL/DLL, rely on the small-signal conductance tracking the large-signal conductance of the voltage-controlled oscillator/voltage-controlled delay-line and, thus, sustain constant /spl omega//sub n///spl omega//sub ref/ and /spl zeta/ only if the voltage swing is sufficiently higher than the device threshold voltage V/sub TH/. The paper also presents procedures to estimate the open-loop parameters from an open-loop impulse response of the PLL/DLL.