The 2D structure and excellent electronic properties of graphene have generated worldwide interest, and offer the potential to overcome the limitations of silicon electronics.1 Early graphene-based devices consisted of a single atomic layer, but the possibility of tailoring electronic properties by stacking several different 2D crystals atop each other has since been discovered.2–5 In the assembly of these multilayer heterostructures, unwanted materials can become trapped between layers, adversely affecting the device quality. Understanding the cause of performance variations and thereby optimizing the properties of these devices is an extremely challenging task.
Carlotta Ciancico, Iacopo Torre, Bernat Terrés, Álvaro Moreno, Robert Smit, Kenji Watanabe, Takashi Taniguchi, Michel Orrit, Frank H. L. Koppens, Antoine Reserbat‐Plantey
Carlotta Ciancico, Iacopo Torre, Bernat Terrés, Álvaro Moreno, Robert Smit, Kenji Watanabe, Takashi Taniguchi, Michel Orrit, Frank H. L. Koppens, Antoine Reserbat‐Plantey
Francesca Falorsi, Shuangjie Zhao, Kejun Liu, Christian Eckel, Jonas F. Pöhls, Wiebke Bennecke, Marcel Reutzel, Stefan Mathias, Kenji Watanabe, Takashi Taniguchi, Zhiyong Wang, Miroslav Položij, Xinliang Feng, Thomas Heine, R. Thomas Weitz
Discussion(0)
No comments yet. Be the first to comment.