Comparative analysis of three interleaved boost power factor corrected topologies in DCM

The aim of this paper is to analyze in a comparative manner three interleaved boost power factor corrected (PFC) topologies that alleviate some of the conventional boost PFC shortcomings like high input current ripple and current stress. A parallel interleaved topology and two novel serial topologies especially suitable for electronic ballast applications are considered. The boost inductor current and size and the input harmonic current are expressed analytically and compared considering the conventional boost PFC as reference. A practical design example is analyzed using the PSPICE computer simulator.