Clustered voltage scaling technique for low-power design

Article Free Access Share on Clustered voltage scaling technique for low-power design Authors: Kimiyoshi Usami Toshiba Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, Japan and Stanford University, Stanford, CA Toshiba Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, Japan and Stanford University, Stanford, CAView Profile , Mark Horowitz Stanford University, Stanford, CA Stanford University, Stanford, CAView Profile Authors Info & Claims ISLPED '95: Proceedings of the 1995 international symposium on Low power designApril 1995 Pages 3–8https://doi.org/10.1145/224081.224083Online:23 April 1995Publication History 338citation1,972DownloadsMetricsTotal Citations338Total Downloads1,972Last 12 Months53Last 6 weeks11 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF