Channel-limited high-speed links: modeling, analysis and design

Today's high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints and noise sources that differ from those in standard communication systems. The bandlimited channels make straight circuit solutions inefficient, and the power constraints make standard digital communication approaches infeasible. This thesis presents a system-level link design approach, integrating the noise and channel properties with communication algorithms and circuit-level power and speed constraints. Our model incorporates accurate statistics of the dominant link noise sources. Mapping the timing noise into effective voltage noise reveals the critical impact of high-frequency transmit jitter. The capacity of typical high-speed link backplane channels is shown to be between 50 and 100 Gb/s, which is much higher than 3 Gb/s data rates of currently deployed baseband links. To improve these practical links, we solve the power-constrained optimal linear precoding problem and formulate a bit-error rate (BER) driven optimization, including all link-specific noise sources and hardware constraints. We show that practical data rates are mainly limited by inter-symbol interference due to complexity constraints on the number of equalizer taps. The slicer resolution and sampling jitter limit the higher bandwidth utilization provided by multi-level modulations. Better circuits could improve this utilization to more than 2 bits/dimension. With current circuit precision, links with both PAM2 and PAM4 modulation, and a combination of transmit pre-emphasis and decision-feedback equalization (DFE) achieve 5–12 Gb/s data rates. With only minor modifications, the hardware needed to implement a PAM4 system can be used in a loop-unrolled single-tap DFE receiver. To get the maximum performance from either technique in practice, the link has to adapt itself to the channel. We designed a low-cost adaptive equalizer using data-based update filtering, which minimizes the required sampler front-end hardware and reduces the implementation cost in multi-level signaling schemes. A transceiver chip was fabricated in a 0.13 μm CMOS process to investigate dual-mode PAM2/PAM4 operation and the modifications of the standard adaptive algorithms necessary to operate in high-speed link environments. The experimental data match the statistical link model predictions extremely well, within a couple of mV, even at BERs lower than the required 10−15.