Canonical piecewise-linear modeling

To take advantage of the remarkable computational efficiency of the canonical piecewise-linear approach for dc nonlinear electronic circuit analysis, the devices must be modeled by a canonical piecewise-linear model. This paper presents a unified parameter optimization algorithm for constructing such models. This algorithm is then applied to derive prototype canonical piecewise-linear models of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p-n</tex> junction diodes, bipolar transistors, MOSFET's, and GaAs FET's. The canonical piecewise-linear model can be regarded as a universal model since its form remains unchanged for all devices. Only the coefficients differ from one device to another. For large-scale circuits, the canonical piecewise-linear representation has a decisive advantage over other representations in regard to the number of memory locations needed to specify the equations.