Journal of Parallel and Distributed Computing 73(11): 1417-1429
Article 2012 English
Authors
SC
Sunita Chandrasekaran
SS
Shilpa Shanbagh
RJ
Ramkumar Jayaraman
Abstract
1 min read
In this paper, we present a design methodology that uses a combined graphical and scheduling technique to map C-based high level language (HLL) based applications to FPGA. Although there are a number of approaches addressing the mapping from HLL to hardware, many of these existing solutions either require a steep learning curve or do not produce an appropriate mapping pattern for the hardware platform. We provide a solution to this problem, by analyzing the data flow and data dependencies in the given code and proposing a scheduling patterns for the given algorithm. We then provide a suitable mapping pattern for the hardware platform. We use the mapping pattern to deliver synthesizable HDL (Verilog) code. We demonstrate our design methodology with results from different real-time case studies that are based on different algorithms.
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