An ordinary synchronous system uses clocks to determine data signal validity. To avoid the problems of distributing high-speed clocks and partitioning logic to fit within clock cycles, asynchronous circuit elements must provide their own completion indication using self-timing. Basic bipolar circuit elements which modify differential current-steering gate styles to achieve completion indication without increasing the number of wires between gate stages and with only about a 50% cost in transistor density per stage are proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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