Binary-Quintuple Progression Based 12-Switch 25-Level Converter With Nearest Level Modulation Technique for Grid-Tied and Standalone Applications

This article introduces a cascaded packed U cell (CPUC) multilevel converter (MLC) to achieve a higher-level count in converter voltage with a minimum number of switches. Here, two five-level packed U cell topologies are connected in a cascaded manner to obtain 25 levels in its output converter voltage. The switch count in CPUC is reduced to 12, as compared to the number of semiconductor devices used for obtaining 25 levels in converter output. A binary-quintuple progression is used for selection of voltage ratios between dc voltage sources and capacitors. CPUC is operated at low-frequency switching, using the nearest level modulation technique. The fundamental switching frequency ensures reduced switching losses as compared to pulsewidth modulation schemes. The converter performance is analyzed for grid-tied and standalone applications. The performance parameters such as total harmonic distortion (THD) of converter voltage and THD of grid/load current are examined. The CPUC configuration is modeled and simulated in MATLAB/Simulink, and test results are taken using OPAL-RT test bench. The acquired simulation and test results confirm viability, practicability, acceptability, and cost-effectiveness of CPUC-MLI converter over existing MLC topologies for efficient power conversion.