Analysis and implementation of an interleaved ZVS bi-flyback converter

The system analysis, circuit implementation and design consideration of interleaved bi-flyback converter with zero voltage switching (ZVS) are presented. To reduce the ripple current on the input and output capacitors and decrease the current stress on the transformer secondary windings, two modules with interleaved pulse-width modulation (PWM) are connected in parallel at the input and output sides. Thus, the transformer copper losses and the conduction losses on the output diodes are reduced. Active snubber is connected in parallel with the main switch to limit the voltage spike because of the transformer leakage inductance when main switch is turned off. All power switches are turned on at ZVS during the commutation stage. Thus, the switching losses and thermal stresses of the semiconductors are reduced. Finally, experiments based on a 720 W (24 V/30 A) prototype are provided to verify the theoretical analysis and the effectiveness of the proposed converter.