A Zero-overhead Self-timed 160ns 54b CMOS Divider

This circuit demonstrates a self-timed iterating ring which attains the speed of a combinational array while using only a fraction of the silicon area. The stages in the ring compute mantissa quotient digits for a floating-point division opera­tion. Unlike circuits which implement self-timing by using a matched on-chip clock generator to provide an internal clock for synchronous blocks, the circuit of this paper uses local control handshaking between fully asynchronous blocks and will operate correctly for any values of gate delays. To avoid requiring matching path delays, completion information is embedded in the data throughout the design by using dual­ monotonic wire pairs. The precharged function blocks use merged n-channel pull-down networks to choose which of the wires in each pair to set high.