A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS
IEEE Journal of Solid-State Circuits 36(11): 1684-1692
Article 2001 English
Authors
CY
Chih-Kong Ken Yang
VS
Vladimir Stojanović
SM
Siamak Modjtahedi
Abstract
1 min read
This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks to within 10 ps, and reduces systematic coupling noise to less than 18 mV on the 800-mV signal swing. 1.1-nH bondwire inductors distribute the parasitic capacitances at the transceiver input and output, reducing attenuation by 10 dB at 4 GHz. Equalization algorithms using the converters compensate for the 1.5-GHz transceiver bandwidth to allow 8-GSamples/s multilevel data transmission.
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