A DC-Link Capacitor Voltage Ripple Reduction Method for a Modular Multilevel Cascade Converter With Single Delta Bridge Cells

This article proposes a capacitor voltage ripple reduction method used for a modular multilevel cascade converter (MMCC) with single delta bridge cells (SDBC), by applying a third harmonic zero-sequence current. A practical case study on an 80 MVar/33 kV MMCC-SDBC-based STATCOM is used to demonstrate the method. The impact of the third harmonic zero-sequence current level of the capacitor ripple reduction and the electrothermal stresses on insulated gate bipolar transistor modules are analyzed. An optimal parameter of the current level is obtained by compromising the above-mentioned performance factors. The obtained result shows that the required capacitance, as well as the capacitor bank volume, is reduced by 20% without increasing the total power semiconductor losses by using the proposed method.