A 32b microprocessor with on-chip 2Kbyte instruction cache

Mark Horowitz; John L. Hennessy; Paul Chow; P.G. Gulak; John M. Acken; Anant Agarwal; Chorng-Yeung Chu; Scott McFarling; Steven A. Przybylski; Stephen Richardson; Arturo Salz; Richard Simoni; D. Stark; Peter Steenkiste; Steve Tjiang; Malcolm J. Wing

doi:10.1109/isscc.1987.1157215

Abstract

1 min read

A Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm×8.5mm chip in a 2μm, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.

Related publications

Article1984

A 20 MIPS Peak Microprocessor with On-Chip Cache,

Mark Horowitz, John L. Hennessy, Paul Chow, P.G. Gulak, John M. Acken

Article1987

MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache

Mark Horowitz, Paul Chow, D. Stark, Richard Simoni, Arturo Salz, Steven A. Przybylski, John L. Hennessy, Glenn Gulak, Anant Agarwal, John M. Acken

IEEE Journal of Solid-State Circuits

Article2011

Replacing a Battery by a Nanogenerator with 20 V Output

Youfan Hu, Long Lin, Yan Zhang, Zhong Lin Wang

Article2015

High Broad‐Band Photoresponsivity of Mechanically Formed InSe–Graphene van der Waals Heterostructures

Garry W. Mudd, Simon A. Svatek, Lee Hague, O. Makarovsky, Z. R. Kudrynskyi, Christopher J. Mellor, Peter H. Beton, L. Eaves, Konstantin ‘kostya’ Novoselov, Z. D. Kovalyuk, Evgeny E. Vdovin, Alexander J. Marsden, Neil R. Wilson, A. Patanè

Advanced Materials

Article2022

Strain-Assisted Single Pt Sites on High-Curvature MoS <sub>2</sub> Surface for Ultrasensitive H <sub>2</sub> S Sensing

Zhenggang Xue, Chun Wang, Yujing Tong, Muyu Yan, Jiangwei Zhang, Xiao Han, Xun Hong, Yafei Li, Yuen Wu