A 0.8 μm CMOS 2.5 Gb/s oversampled receiver for serial links

The demand for higher bit rates by the communications industry has led to the development of high bit rate and low cost serial link interface chips. Recently, interest has grown in using modest CMOS technology to achieve similar bit rates. This work achieves SONET OC-48 (2.488 Gbps) rates with 0.8 /spl mu/m CMOS technology. Because the data rate is near the process unity-gain frequency, a parallel architecture is used to demultiplex the data stream at the input. N precisely-spaced clocks that run at 1/N of the data rate are used. Instead of a conventional analog PLL that would require low noise sensitivity, this work explores oversampling each data bit and using digital logic to select the proper bit values. Although data is not sampled at the center of the eye, the digital loop can choose the best sample with bandwidth roughly the data transition rate.