A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

A 10-Gb/s serial link transmitter fabricated in the LSI 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PAM) and a 3-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the maximum on-chip frequency set by process limitations, a 5:1 output multiplexer is used to reduce the required clock frequency to 1/5 the symbol rate. With a 3.3-V supply, the chip shows an eye opening of >200 mV after a 10-m coaxial cable in simulations.