2,497 publications from this institution
FIGURE 4. Elytral apices of Canidia species: a, C. cincticornis cincticornis Thomson; b, C. cincticornis balteata (Lacordaire); c, C. turnbowi Wappes and Lingafelter; d, C. canescens (Dillon); e, C. mexicana Thomson; f, C. spinicornis (Bates); g, C. giesberti Wappes and Lingafelter; h, C. chemsaki Wappes and Lingafelter.
This paper presents a digital power supply controller for variable frequency and voltage circuits. By using a ring oscillator as a method of predicting circuit performance, the regulated voltage is set to the minimum required to operate at a reference frequency which maximizes energy efficiency. Our initial test silicon, implemented with a fixed frequency controller is analyzed and reveals that the controller's power consumption is a major limitation for such a design. To make the controller power dissipation scale with the CV/sup 2/f power of the load, we introduce a new architecture with variable frequency control, which allows the controller's supply and frequency to scale along with the load device.
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to address this problem successfully in specific situations. However, the generality of these software approaches has been limited because current architectures do not provide a fine-grained, low-overhead mechanism for observing and reacting to memory behavior directly. To fill this need, we propose a new class of memory operations called informing memory operations, which essentially consist of a memory operation combined (either implicitly or explicitly) with a conditional branch-and-link operation that is taken only if the reference suffers a cache miss. We describe two different implementations of informing memory operations---one based on a cache-outcome condition code and another based on low-overhead traps---and find that modern in-order-issue and out-of-order-issue superscalar processors already contain the bulk of the necessary hardware support. We describe how a number of software-based memory optimizations can exploit informing memory operations to enhance performance, and look at cache coherence with fine-grained access control as a case study. Our performance results demonstrate that the runtime overhead of invoking the informing mechanism on the Alpha 21164 and MIPS R10000 processors is generally small enough to provide considerable flexibility to hardware and software designers, and that the cache coherence application has improved performance compared to other current solutions. We believe that the inclusion of informing memory operations in future processors may spur even more innovative performance optimizations.
In the mid 1980's the power growth that accompanied scaling forced the industry to focus on CMOS technology, and leave nMOS and bipolars for niche applications. Twenty years later, CMOS technology is facing power issues of its own. After first reviewing the "cause" of the problem, it will become clear that there are not easy solutions this time -- no new technology or simple system/circuit change will rescue us. Power, and not number of devices is now the primary limiter of chip performance, and the need to create power efficient designs is changing how we do design. In the past, we would turn to specialized computation (ASICs) to create the needed efficiency, but the rising NRE costs for chip design (now over $10M/chip) has caused the number of ASIC design starts to fall not rise.
In the first 2 articles of this series, we reviewed the basic genetics concepts necessary to understand genetic association studies, and we enumerated the major issues in judging the validity of these studies. In this third article, we review the issues relating to the applicability of the results in the clinical situation. How large and precise are the associations? Many genetic effects are expected to be smaller in magnitude than traditional risk factors. Does the genetic association improve predictive power beyond easily measured clinical variables? In some cases, the additional genetic information adds only a small increment in the predictive ability of a diagnostic or prognostic test. What are the absolute vs relative effects? Even if the genetic risk is high in relative terms, the baseline risk may be very low in absolute terms. Is the risk-associated allele likely to be present in my patient? A risk allele may have a strong effect but be rare in a particular ethnic group. Is the patient likely better off knowing the genetic information? Given that genes cannot be modified, one must weigh whether the genetic information is likely to be helpful in planning other health interventions or initiating behavior change.
Dataset and analysis scripts for Cristea, I.A., Georgescu, R., Ioannidis, J.P.A.I. (2021) "Effect Sizes Reported in Highly Cited Emotion Research Compared With Larger Studies and Meta-Analyses Addressing the Same Questions"<br>
We consider the problem of Mobile Internetworking, that is, providing network access to hosts whose physical location changes with time. Such hosts cannot depend on traditional forms of network connectivity and routing, because their location, and hence the route to reach them, cannot be immediately deduced from their network address. The three major points of the thesis, which are a departure from previous approaches, are: ffl Mobility is a network-layer problem, and is best attacked by embedding virtual mobile networks at the proper hierarchical address level. ffl Locality in host mobility, can be taken advantage of in order to yield efficient and practical tracking and routing mechanisms. ffl On-demand acquisition of mobile host location information, which is essentially routing information, yields a system that scales linearly as a function of its size. This dissertation shows the design, implementation and evaluation of IP-based protocols for mobile internetworking. The p...
An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear PLL with a loop bandwidth >30 MHz, phase margin >48/spl deg/ and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8-Gbps data is successfully detected by the receiver after a 10-m coaxial cable. The 2 mm/spl times/2 mm chip consumes 1.1 W at 8 Gbps with a 3-V supply.
