2,497 publications from this institution
The quantity and quality of scientific research have never been greater, but with unprecedented promise comes unprecedented peril.There are better scientific policies and processes, stronger standards for openness and transparency, and innovative technologies to collaborate and publish.However, the rapidly evolving scientific publication ecosystem that facilitates research dissemination also enables research waste, predation, and piracy.The challenge of distinguishing information from noise, innovation from dystopian-like disruption, and opportunity from threat has created new levels of excitement and angst for those engaged in research and its reporting, publication, and distribution.In these historically challenging circumstances, we announce the ninth international congress on peer review and scientific publication, which will take place on 12-14 September 2021 in Chicago, Illinois.Since the first peer review congress in 1989, founded by Drummond Rennie when he was JAMA's deputy editor, 1 the aim has been to encourage research into the quality and credibility of peer review and scientific publication.The goal is to strengthen the evidence base so that all those involved in science (including but not limited to researchers, editors, publishers, funders, policy makers, academics, and representatives of universities, industry, media, and the general public) can improve the conduct, reporting, and dissemination of scientific research. 2 A few core principles and practices have governed past congresses and the next one announced here. 3 The congresses provide a forum for research into the processes of selection, refinement, and dissemination of scientific knowledge.They do not presume
Modem, high performance microprocessors are extremely complex machines which require substantial validation effort to ensure functional correctness prior to tapeout. Generating the corner cases to test these designs is a mostly manual process, where completion is hard to judge. Experience shows that the errors that are caught late in the design, many post-silicon, are interactions between different components in very improbable corner case situations. In this paper we present a technique that targets such error-causing interactions by automatically generat- ing test vectors that will cause the processor to exercise all transitions of the control logic in simulation. We use techniques from formal verification to derive transition tours of a fully enumerated state graph of the control logic of the processor. Our system works from a Verilog description of the original machine and is currently being used to validate an embedded dual-issue processor in the node controller of the Stanford FLASH Multiprocessor. Modeling the processor control results in 200K states and an 8M instruction trace to check all transitions of control arcs.
The increasing speed of new generation processors will exacerbate the already large difference between CPU cycle times and main memory access times. As this difference. grows, it will be increasingly difficult to build single-level caches that are both fast enough to match these fast cycle times and large enough to effectively hide the slow main memory access times. One solution to this problem is to use a multi-level cache hierarchy. This paper examines the relationship between cache organization and program execution time for multi-level caches. We show that a first-level cache dramatically reduces the number of references seen by a second-level cache, without having a large effect on the number of second-level cache misses. This reduction in the number of second-level cache hits changes the optimal design point by decreasing the importance of the cycle-time of the second-level cache relative to its size. The lower the first-level cache miss rate, the less important the second- level cycle time becomes. This change in relative importance of cycle time and miss rate makes associativity more attractive and increases the optimal cache size for second-level caches over what they would be for an equivalent single-level cache system.
Our website uses cookies to enhance your experience. By continuing to use our site, or clicking "Continue," you are agreeing to our Cookie Policy | Continue JAMA HomeNew OnlineCurrent IssueFor Authors Publications JAMA JAMA Network Open JAMA Cardiology JAMA Dermatology JAMA Health Forum JAMA Internal Medicine JAMA Neurology JAMA Oncology JAMA Ophthalmology JAMA Otolaryngology–Head & Neck Surgery JAMA Pediatrics JAMA Psychiatry JAMA Surgery Archives of Neurology & Psychiatry (1919-1959) Podcasts Clinical Reviews Editors' Summary Medical News Author Interviews More JN Learning / CMESubscribeJobsInstitutions / LibrariansReprints & Permissions Terms of Use | Privacy Policy | Accessibility Statement 2023 American Medical Association. All Rights Reserved Search All JAMA JAMA Network Open JAMA Cardiology JAMA Dermatology JAMA Forum Archive JAMA Health Forum JAMA Internal Medicine JAMA Neurology JAMA Oncology JAMA Ophthalmology JAMA Otolaryngology–Head & Neck Surgery JAMA Pediatrics JAMA Psychiatry JAMA Surgery Archives of Neurology & Psychiatry Input Search Term Sign In Individual Sign In Sign inCreate an Account Access through your institution Sign In Purchase Options: Buy this article Rent this article Subscribe to the JAMA journal
Coronary Sinus Mapping. Introduction: Striated myocardial connections between the venous wall of the coronary sinus (CS) and the left atrium have been described in humans. This aim of this study was to investigate the conduction properties and potential arrhythmogenicity of CS and left atrial myocardial connections in patients with and patients without paroxysmal atrial fibrillation (PAF). Methods and Results: Thirty‐eight patients with PAF, 52 patients with other arrhythmias, and 44 patients without arrhythmia underwent catheter mapping of the CS from the distal superoposterior part to the ostium. Catheterization of the superoposterior CS was feasible in 21, 32, and 25 subjects in the three groups, respectively ( P = 0.82 ). Discrete double potentials or fractionated electrograms were recorded during proximal CS or right atrial pacing in 14 (66.7%), 11 (34.4%), and 5 (20.0%) patients, respectively ( P = 0.004 ). In 29 patients, double or fractionated potentials were recorded at the distal superoposterior CS, in 3 at the mid‐CS, and in 4 at the ostium. Spontaneous or induced atrial ectopy and/or tachyarrhythmias were recorded in 18 (85.7%), 12 (37.5%), and 2 (8.0%) patients in the three groups, respectively ( P < 0.001 ) and originated from the CS in 6, 3, and 0 patients, respectively ( P = 0.010 ). Conclusion: Recording of double potentials is possible within the CS, particularly at its distal superoposterior part, near the left superior pulmonary vein. Their prevalence is higher in patients with PAF than in subjects with other or no arrhythmias, and their presence denotes possible sources or substrate for atrial arrhythmia.
Naïve lists of international institutional rankings that do not address these fundamental challenges with transparent methods are misleading and should be abandoned. We make some suggestions on how focused and standardized evaluations of excellence could be improved and placed in proper context.
In this viewpoint we discuss a potential financial conflicts of interest relevant to psychosocial interventions and suggest ways to improve disclosure.
Our website uses cookies to enhance your experience. By continuing to use our site, or clicking "Continue," you are agreeing to our Cookie Policy | Continue JAMA HomeNew OnlineCurrent IssueFor Authors Publications JAMA JAMA Network Open JAMA Cardiology JAMA Dermatology JAMA Health Forum JAMA Internal Medicine JAMA Neurology JAMA Oncology JAMA Ophthalmology JAMA Otolaryngology–Head & Neck Surgery JAMA Pediatrics JAMA Psychiatry JAMA Surgery Archives of Neurology & Psychiatry (1919-1959) Podcasts Clinical Reviews Editors' Summary Medical News Author Interviews More JN Learning / CMESubscribeJobsInstitutions / LibrariansReprints & Permissions Terms of Use | Privacy Policy | Accessibility Statement 2023 American Medical Association. All Rights Reserved Search All JAMA JAMA Network Open JAMA Cardiology JAMA Dermatology JAMA Forum Archive JAMA Health Forum JAMA Internal Medicine JAMA Neurology JAMA Oncology JAMA Ophthalmology JAMA Otolaryngology–Head & Neck Surgery JAMA Pediatrics JAMA Psychiatry JAMA Surgery Archives of Neurology & Psychiatry Input Search Term Sign In Individual Sign In Sign inCreate an Account Access through your institution Sign In Purchase Options: Buy this article Rent this article Subscribe to the JAMA journal
: This investigation considers the relationship between the physical failures that occur during fabrication and the resulting faulty behavior of the circuit. Fault models are used to describe the operation of integrated circuits containing physical failures introduced during fabrication. The effectiveness of fault models is dependent upon both the accuracy of the model and the occurrence of the underlying failure mechanism. A specially designed static RAM provides the size, design style, and testability required of a fault model test bed. An actual RAM implementation is described which was used for evaluation of fault models.